Among the typical tests that are performed on SRAM arrays are tests for memory cell data retention faults (DRFs) and memory cell stability faults. In particular, DRFs and stability faults often result from variations in manufacturing materials and processes. In the past, DRF and stability fault testing has been largely functional in nature. Namely, a read/write algorithm is developed that functionally exercises the SRAM. The read/write algorithm is then executed by a memory test system external to the IC. From the results of the functional testing, an attempt is made to deduce DRFs and stability faults for individual memory cells in the SRAM.
Recently, several test methodologies have been developed that directly test for such failures instead of inferring the failures from functional tests. Moreover, some of these test methodologies are well-suited to being implemented as a built-in self-test (BIST), such that the cost and time associated with testing for DRF and stability faults using an external memory test system are reduced or effectively eliminated. One such methodology known as Weak Write Test Mode (WWTM) is disclosed by Banik et al., U.S. Pat. No. 5,559,745, incorporated herein by reference.
When testing an SRAM with WWTM, an attempt is made to overwrite a data value stored in a memory cell using a “weak” write value or signal. The weak write signal is only capable of overwriting the stored value in the memory cell if the memory cell is unstable or defective. Thus, if the weak write test is successful, a defect in the memory cell is indicated. An unsuccessful weak write test indicates a healthy memory cell, at least with respect to stability and DRFs.
Weiss et al., U.S. Pat. No. 6,192,001 B1, incorporated herein by reference, disclose a WWTM approach that integrates a weak write driver functionality into an existing conventional column-associated write driver of the SRAM. According to Weiss et al., only two additional transistors are added to each conventional write driver in each set of columns as opposed to six transistors per column according to Banik et al. A set of columns is one or more columns depending on whether or not column multiplexing is employed in the SRAM. In particular, a first or weak write pull-down transistor is added that modifies a level of an output signal of the write driver when in WWTM and a second or bypass pull-down transistor is added that essentially bypasses the first transistor thereby facilitating a normal or strong write output signal to be produced by the write driver when not in WWTM.
Unfortunately, sizing of the weak write pull-down transistor of Weiss et al. presents certain practical difficulties in IC manufacturing. In particular, the weak write pull-down transistor must be big or strong enough to insure that the WWTM write driver output signal adequately exercises the memory cells of the SRAM, allowing for reliable detection of defective memory cells. Simultaneously, the weak write pull-down transistor must be small or weak enough such that the WWTM write driver output signal is not capable of overwriting data in healthy memory cells thereby producing false detection of defects.
In practice, the weak write pull-down transistor sizing is sensitive to variables and tolerances of a given manufacturing line and/or inadequacies of a design simulation to account for such variables and tolerances. Thus, many memory design and prototype iterations may be necessary to produce a properly sized weak write pull-down transistor. Moreover, each time the IC design is changed and/or the manufacturing process/line is changed or modified, the iterative design process typically must be repeated.
Accordingly, it would be advantageous to have a way to implement WWTM that was less sensitive to weak write pull-down transistor sizing. In addition, it would be advantageous if such implementations did not appreciably increase the number of transistors in the SRAM array or a number of traces in the SRAM IC used to access and activate WWTM. Such an implementation of WWTM would solve a long-standing need in the area of BIST for ICs that contain SRAM arrays.